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general description the MAX555 is an advanced, monolithic, 12-bit digital- to-analog converter (dac) with complementary 50 ? outputs. fabricated using an oxide-isolated bipolar process, the MAX555 is designed for signal-reconstruc- tion applications at an output update rate of 300msps. it incorporates an analog multiplying function with 10mhz useable input bandwidth. the voltage-output dac uses precision laser trimming to achieve 12-bit accuracy with ?/2lsb integral and differential linearity (?.012% fs). absolute gain error is a low 1% of full scale. full-scale transitions occur in less than 0.5ns. internal registers and a unique decoder reduce glitch- ing and allow the MAX555 to achieve precise rf perfor- mance with over 73dbc of spurious-free dynamic range at 50msps with f out = 3.1mhz, or 62dbc at 300msps with f out = 18.6mhz. the MAX555 operates from a single -5.2v supply and dissipates 980mw (nominal). it comes in a 64-pin tqfp package with exposed paddle for enhanced thermal dissipation. ________________________applications direct digital synthesis arbitrary waveform generation hdtv/high-resolution graphics instrumentation communications local oscillators automated tester applications ____________________________features 12-bit resolution 1/2lsb integral and differential nonlinearity capable of 300msps (min) update rate complementary 50 ? outputs multiplying reference input low glitch energy (5.6pvs) single -5.2v power supply on-chip data registers ecl-compatible inputs with differential clock ordering information MAX555 300msps, 12-bit dac with complementary voltage outputs ________________________________________________________________ maxim integrated products 1 -20ma lgnd vout vout clk clk roffset ref 50 ? 800 ? 800 ? 50 ? av ee bypass decoded bit lines 12-bit ecl lines level-sensitive transparent latch MAX555 ___________________________________________________simplified block diagram 19-0297; rev 3; 6/02 part MAX555ccb 0? to +70? temp range pin-package 64 tqfp-ep* pin configuration appears at end of data sheet. evaluation kit manual available for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * ep = exposed pad.
MAX555 300msps, 12-bit dac with complementary voltage outputs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av ee = dv ee = -5.2v, v ref = 1.000v, t min to t max = 0? to +70?, unless otherwise noted.) (note 2.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: typical thermal resistance, junction-to-case r jc = 25?/w. see package information. analog supply voltage (av ee ) .................................-7v to +0.3v digital supply voltage (dv ee ) ..................................-7v to +0.3v digital input voltage (d0?11) ...................................-5.5v to 0v reference input voltage (v in ) .................................0v to +1.25v reference input current....................................0ma to +1.56ma output compliance voltage (v oc )......................-1.25v to +1.0v output common-mode voltage (v cm ) ................-0.25v to +1.0v continuous power dissipation (t a = +70?) (without additional heatsink) ..............................................1.3w operating temperature range...............................0? to +70? junction temperature range (note 1) .................0? to +150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? v ref = 1.000v, current out, into virtual ground, end-point linearity major carry, t a = +25? 10% to 90%, t a = +25? 90% to 10%, t a = +25? v ref = 1.000v, voltage out, vout /vin (note 3) ?.024% fs, 1lsb change d0?11 = logic 1, v ref = 1.000v, measured at vout ?.1% fs conditions ns 15 settling time 4 % fs -0.05 ?.01 0.05 dle2 differential linearity error -0.012 ?.003 0.012 dle1 pvs 5.6 glitch energy ps 570 t rise rise time ps 410 t fall fall time % fs -1.0 ?.2 +1.0 ge absolute gain error guaranteed 12-bit monotonicity ? 40 100 i os output offset current units min typ max symbol parameter vout vout v ref = 1.000v, current out, into virtual ground, end-point linearity vout % fs -0.05 ?.01 0.05 ile2 integral linearity error vout -0.012 ?.006 0.012 ile1 d0?11 = logic 0, v ref = 0v, measured at vout ? 350 i leak output leakage current f out = 5mhz, f clk = 50mhz 72 f out = 20mhz, f clk = 100mhz f out = 10mhz, f clk = 50mhz 63 68 f out = 30mhz, f clk = 200mhz f out = 30mhz, f clk = 100mhz 57 58 f out = 40mhz, f clk = 200mhz 54 dbc f out = 40mhz, f clk = 250mhz 53 f out = 40mhz, f clk = 300mhz f out = 50mhz, f clk = 250mhz 54 51 f out = 50mhz, f clk = 300mhz sfdr spurious-free dynamic range 51 nv hz bits 0?1 high, t a = +25? 10.6 output noise dc accuracy time-domain performance (note 4) dynamic performance (notes 4, 5)
MAX555 300msps, 12-bit dac with complementary voltage outputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (av ee = dv ee = -5.2v, v ref = 1.000v, t min to t max = 0? to +70?, unless otherwise noted.) (note 2.) av ee = dv ee = -5.2v av ee = dv ee = -5.2v v il = -1.95v vout, vout vout, vout v ih = -0.75v v ref = 1.000v, r l = 0 ? t a = +25? t a = +25? bypass = 1, transparent mode (notes 4, 7) bypass = 1, transparent mode (notes 4, 7) -3db v ref = 1.000v bypass = 0, clocked mode (notes 4, 7) bypass = 0, clocked mode (notes 4, 7) bypass = 0, clocked mode (notes 4, 7) bypass = 1, transparent mode (notes 4, 7) conditions ma 110 150 190 di ee digital power-supply current ma 30 46 60 ai ee analog power-supply current pf 15 c out output capacitance ? 49.5 50.0 50.5 r out output resistance ma 19.0 20.0 21.0 i out full-scale output current ? -250 0 +250 v os input offset voltage kv/v 320 av ol open-loop gain mhz 10 bw multiplying input bandwidth ? 775 800 825 r in amplifier input resistance ps 900 t dd msbs decode delay ? 12 i il input current, logic low ? 10 200 i ih input current, logic high ns 2.9 t pd1 msbs data-to-vout propagation delay ns 2 t pd2 lsbs data-to-vout propagation delay ns 2.8 t pd3 clock-to-vout propagation delay ns 0.8 t hold data-to-clock hold time v -1.1 -0.75 0 v ih logic "1" voltage v -2.0 -1.95 -1.48 v il logic "0" voltage ns 1 t su data-to-clock setup time units min typ max symbol parameter w 0.98 1.3 p diss power dissipation ?/w 25 t ja package thermal resistance, junction to ambient note 2: all devices are 100% production tested at +25? and are guaranteed by design for t a = t min to t max as specified. note 3: the gain-error method of calculation is shown below: definition: [v measure(fs) - v ideal(fs) ] x 100 ge(%) = v ideal(fs) where fs indicates full-scale measurements. ge method: ge(%) = [(4096 / 4095) v measure - 16(v ref / r in ) (r out )] x 100 16(v ref / r in ) (r out ) = [(4096 / 4095) v measure - 1] x 100 1 where: v ref = 1.000v, r in = 800 ? , r out = 50 ? , v measure = vout (fs). note 4: dynamic and timing specifications are obtained from device characterization and simulation testing and are not production teste d. note 5: spurious-free dynamic range is measured from the fundamental frequency to any harmonic or nonharmonic spurs within the bandwidth f clk /2, unless otherwise specified. note 6: guaranteed by design. note 7: timing definitions are detailed in figure 2. minimum data rate = dc (note 6) mhz 300 f d data update rate digital inputs control amplifier output performance power supplies digital timing
MAX555 300msps, 12-bit dac with complementary voltage outputs 4 _______________________________________________________________________________________ __________________________________________typical operating characteristics (av ee = dv ee = -5.2v, v ref = 0.75v, t a = +25?, unless otherwise noted.) 62 66 64 70 68 72 74 08 4121620 spurious-free dynamic range vs. f out (f clk = 50mhz) MAX555-01 f out (mhz) sfdr (dbc) 60 64 62 68 66 72 70 74 0812 4 16202428 spurious-free dynamic range vs. f out (f clk = 100mhz) MAX555-02 f out (mhz) sfdr (dbc) 50 54 62 58 66 70 012 6 18243036 spurious-free dynamic range vs. f out (f clk = 150mhz) MAX555-03 f out (mhz) sfdr (dbc) 74 spurious-free dynamic range vs. f clk (f out ~ 1/16 f clk ) 58 70 MAX555-07 clock frequency (mhz) sfdr (db) 350 300 250 200 150 100 50 66 62 60 72 68 64 -48 0.5 0.6 0.7 0.8 0.9 1.0 3rd harmonic distortion vs. v ref voltage (f out ~ 1/5 f clk ) -52 MAX555-08 v ref (v) 3rd harmonic (dbc) -56 -50 -54 -58 -60 -62 -64 -66 -68 -70 -72 f clk = 100mhz f clk = 200mhz f clk = 300mhz -48 0.5 0.6 0.7 0.8 0.9 1.0 2nd harmonic distortion vs. v ref voltage (f out ~ 1/5 f clk ) -52 MAX555-09 v ref (v) 3rd harmonic (dbc) -56 -50 -54 -58 -60 -62 -64 -66 -68 -70 -72 f clk = 100mhz f clk = 200mhz f clk = 300mhz 52 56 64 60 68 72 012 6 18243036 spurious-free dynamic range vs. f out (f clk = 200mhz) MAX555-04 f out (mhz) sfdr (dbc) 52 56 64 60 68 72 014 7 21283542 spurious-free dynamic range vs. f out (f clk = 250mhz) MAX555-05 f out (mhz) sfdr (dbc) 50 54 62 58 66 70 020 10 30 40 50 60 spurious-free dynamic range vs. f out (f clk = 300mhz) MAX555-06 f out (mhz) sfdr (dbc)
MAX555 300msps, 12-bit dac with complementary voltage outputs _______________________________________________________________________________________ 5 _______________detailed description figure 1? functional diagram shows the MAX555? three major divisions: a digital section, a control-amplifier sec- tion, and a resistor-divider network. the digital section consists of a master/slave register, decoding logic, and current switches. the control-amplifier section includes a control amplifier and an array of 23 current sources divid- ed into three groups. the resistor divider scales the cur- rents from these groups to achieve the correct binary weighting at the output. the output of the resistor-divider network is laser trimmed to 50 ? , a key feature for driving into controlled impedance transmission lines. the first group of current sources comprises the six msbs, d11?6 (resulting in 15 identical, plus two binary pin description pin name function 1, 14, 16 19, 27, 28, 29, 31 38, 48, 49, 64 agnd analog ground. note: exposed pad on the back of the package must be connected to agnd. 2, 6, 54, 60 dgnd digital ground 3 d8 data bit 8 (ecl input) 4 d9 data bit 9 (ecl input) 5 d10 data bit 10 (ecl input) 7, 53 dv ee -5.2v digital power supply 8 d11 data bit 11 (ecl input) msb 9, 10, 11, 13, 39, 46, 58 n.c. no connection 12 lbias ladder-bias alternate compensation output. connect bypass capacitor to av ee . 15 altcompc control-amplifier ptat reference compensation input. connect bypass capacitor to av ee . 20 roffset offset compensation input 21, 22 ref analog reference voltage inputs (kelvin connection) 23 ref/2 analog reference voltage center-tap input 24, 25 av ee -5.2v analog power supply 26 loopcrnt test node. must connect to agnd. 30 altcompib ptat-ib reference compensation output. connects bypass capacitor to av ee . 40, 41 vout complementary dac output 42, 43 lgnd ladder ground 44, 45 vout dac output 47 d0 data bit 0 (ecl input) lsb 50 d1 data bit 1 (ecl input) 51 d2 data bit 2 (ecl input) 52 d3 data bit 3 (ecl input) 55 clk complementary clock input (ecl input) 56 clk clock input (ecl input) 57 bypass disables latching of data when high (ecl input) 59 d4 data bit 4 (ecl input) 61 d5 data bit 5 (ecl input) 62 d6 data bit 6 (ecl input) 63 d7 data bit 7 (ecl input)
MAX555 weighted currents), which are applied directly to the out- put of the resistor-divider network. the second group, bits d5 d3 (three binary weighted currents), is applied to the middle of the divider network. the middle of the network divides the current seen at the output by 8. the third group, bits d2 d0 (three additional binary weighted current sources), is applied to the input of the resistive network, dividing the current seen at the output by 64. glitching is reduced by decoding the four msbs into 15 identical current sources and synchronizing data with a master/slave register at every current switch. data bits are transferred to the output on the positive-going edge of the clock, with the bypass input asserted low. in the asynchronous mode with the bypass input asserted high, the latches are transparent and data is trans- ferred to the output regardless of the clock state. all digital inputs are ecl compatible. the clock input is differential. the control amplifier forces a reference current, which is replicated in the current sources. this reference current is nominally 1.25ma. it can be supplied by an external cur- rent source, or by an external voltage source of 1.000v applied to the ref input. a reference input of v ref = 1.000v will produce a full- scale output voltage of v fs = -1.000v, where: v fs = 4096 / 4095 x vout (code 0) for the vout output. the output coding is summarized in table 1. 300msps, 12-bit dac with complementary voltage outputs 6 _______________________________________________________________________________________ MAX555 lgnd vout vout 50 ? 800 ? 800 ? 400 ? 400 ? 50 ? i1 i2 8 8 io i3 3 4 2 15 15 8 8 i1 8 8 3 3 17 i2 i3 3 17 4 to 15 decoder current sources and switching network slave register master register 12 inputs dgnd agnd av ee dv ee lbias control amplifier i = v in /r in resistor-divider network msb (d11) clk clk bypass ref/2 ref (1v fs) roffset lsb (d0) altcompib altcompc loopcrnt av ee io digital section figure 1. functional diagram
MAX555 300msps, 12-bit dac with complementary voltage outputs _______________________________________________________________________________________ 7 the dac s control amplifier has a typical open-loop volt- age gain of 85db, and its gain-magnitude bandwidth is flat up to 10mhz. when the control amplifier is not being used for high-speed multiplying applications, it is recom- mended that a 0.4f capacitor be connected from lbias to av ee to increase control-amplifier stability and reduce current-source noise. timing information the MAX555 features a differential ecl clock input with selective transparent operation (bypass = 1). it is possi- ble to drive the MAX555 clock single-ended if desired by tying the clk input to an external voltage of -1.3v (ecl v bb ). however, using a differential clock provides greater noise immunity and improved dynamic performance. in clocked mode (bypass = 0), when the clock line is low, the slave register is locked out and information on the digital inputs is permitted to enter the master regis- ter. the clock transition from low to high locks the mas- ter register in its present state and ignores further changes on the digital inputs. this transition simultane- ously transfers the contents of the master register to the slave register, causing the dac output to change. figure 2 s timing diagram illustrates the importance of operating the MAX555 in clocked mode. in transparent mode (bypass = 1), both the master and slave registers are transparent, and changes in input data ripple directly to the output. because the four msbs are decoded into 15 identical currents, there is a decode delay for these bits that is longer than for the eight lsbs. for the full- scale transition case shown, an intermediate output of 1/16 full-scale occurs until the four msbs are properly decoded. this decode delay seriously degrades the device s spurious performance. in addition, skew in the timing of the input data also directly appears at the dac output, further degrading high-speed performance. MAX555 operation in the clocked mode (bypass = 0) with a differential clock precludes both of these poten- tial problems and is required for high-speed operation. since input data can only enter the master register when the clock is low (while the slave register is locked out), data-bus timing skew and the internal msb decode delay will not appear at the dac output. the dac currents are switched only when the clock transi- tions from low to high, after the internal data stabilizes. layout and power supplies the MAX555 has separate pins for analog and digital supplies. av ee and dv ee are connected to each other through the substrate of the ic. these potentials should be derived from the same supply to minimize voltage mismatch, which can cause substrate current flow and vout transparent mode bypass = 1 clocked mode bypass = 0 d0 d11 vout d0 d11 clk vout vout t su t dd f.s. t pd2 16 15 f.s. 16 1 t hold t pd3 t pd1 figure 2. timing diagram table 1. output coding 100000000000 -0.499756 -0.500000 011111111111 -0.500000 -0.499756 vout (v) vout (v) 000000000000 -0.999756 0 digital code (d11?0) 111111111111 0 -0.999756 000000000001 -0.999512 -0.000244
MAX555 300msps, 12-bit dac with complementary voltage outputs 8 _______________________________________________________________________________________ possible latchup. appropriate decoupling is needed to prevent digital-section current spikes from affecting the analog section (figure 4). it is recommended that a multilayer pc board be used, containing a solid ground and power planes. all analog and digital ground pins must be connected directly to the analog ground plane at the MAX555, preferably with a star connection at the lgnd pins (15 and 16). high-speed ecl inputs, as well as the output from the MAX555, should employ good transmission-line tech- niques, with terminations close to the device pins. separate power-supply buses for analog and digital power supplies are recommended as good general practice. best results will be achieved by bypassing the device pins with high-quality ceramic chip capaci- tors connected physically close to the pins. applications information reference input the MAX555 uses an internal op-amp circuit to buffer the reference current. the input to the op amp may be driv- en with an external current source of 1.25ma or a 1v external voltage reference. the reference input is the ref pin. the input impedance to the op amp is 800 ? . as shown in figure 1, ref/2 is brought out externally with 400 ? of impedance to the op amp. these reference inputs can be used to vary the full-scale output for high- speed multiplying applications. roffset must be con- nected to analog ground. in addition, a 0.1f capacitor should be connected from ref/2 to analog ground to reduce reference current noise. outputs the analog outputs are laser trimmed to 50 ? . they can be used either as a voltage drive with 50 ? impedance, or to drive into a virtual null using a transimpedance amplifi- er. greater speed is achieved driving into 50 ? loads. the differential outputs of the MAX555 may be used to drive a balun for conversion to a single-ended output, while at the same time greatly reducing the second-har- monic content of the output. dynamic performance the typical operating characteristics graphs show the MAX555 s performance when used in direct digital synthe- sis (dds) applications for generating rf sine waves. the first six graphs show the m ax555 s spurious-free dynam- ic range (sfdr) for clock frequencies of 50mhz to 300mhz at various output frequencies. the seventh graph displays the sfdr for clock frequencies from 50mhz to 350mhz while producing an output frequen- cy of about 1/16 the clock frequency. the last two graphs show the MAX555 s third and sec- ond harmonic distortion while producing an output fre- quency of about 1/5 f clk for clock frequencies from 100mhz to 300mhz as a function of the reference volt- age. the third harmonic content of the output can be reduced at clock frequencies below about 200mhz by reducing the reference voltage from its 1.000v nominal value. at clock frequencies above about 200mhz, the output s third harmonic content is dominated by cou- pling from the high-speed digital inputs to the output. reducing the reference voltage at these high clock rates increases the third harmonic distortion in the out- put, since the carrier amplitude drops but the third har- monic level remains relatively constant. the second harmonic distortion of the outputs is shown as a function of clock frequency and reference voltage. it is relatively constant for clock frequencies below about 200mhz at different v ref values. as with the third harmonic distortion, however, the second harm- onic distortion also increases at clock frequencies over 200mhz for lower v ref values. reducing the swing of the input logic levels and/or decreasing the rise time of the digital signals can improve the output s harmonic content. some experimentation may be required to optimize the MAX555 s performance for a particular application. figure 3 shows the spectrum analyzer plots of the MAX555 when used in dds applications. these plots show the MAX555 s output spectrum at clock frequen- cies from 50mhz to 300mhz while producing various output frequencies. observing the output spectrum while adjusting the reference voltage or varying the logic levels is a sensitive method of optimizing MAX555 performance. the plots shown were obtained with a 0.75v reference voltage level and 500mv ecl logic swings. typical application figure 4 shows a typical connection. with vout used to drive a 50 ? line, the unused complementary output, vout, should also be terminated to 50 ? . a 1v refer- ence voltage at ref gives a -0.5v full-scale voltage at vout (when doubly terminated with 50 ? on the out- put). because some loads may represent a complex impedance, be sure to match the output impedance with the load. mismatching the impedances can cause reflections that will affect ac-performance parameters. in all applications, the loopcrnt pin is always con- nected to agnd, and compensation capacitors are connected to pins altcompc, altcompib, and lbias. the lbias compensation is recommended for non-multiplying applications.
MAX555 300msps, 12-bit dac with complementary voltage outputs _______________________________________________________________________________________ 9 figure 3. spectrum analyzer plots 2.3mhz/div -1 -11 -21 -31 -41 -51 dbm -61 -71 -81 output spectrum (f out = 5mhz, f clk = 50mhz) 7mhz/div output spectrum (f out = 9.3mhz, f clk = 150mhz) -1 -11 -21 -31 -41 -51 dbm -61 -71 -81 4.5mhz/div output spectrum (f out = 24mhz, f clk = 100mhz) -1 -11 -21 -31 -41 -51 dbm -61 -71 -81 9.5mhz/div output spectrum (f out = 30mhz, f clk = 200mhz) -1 -11 -21 -31 -41 -51 dbm -61 -71 -81 15mhz/div output spectrum (f out = 55mhz, f clk = 300mhz) -1 -11 -21 -31 -41 -51 dbm -61 -71 -81 12mhz/div output spectrum (f out = 20mhz, f clk = 250mhz) -1 -11 -21 -31 -41 -51 dbm -61 -71 -81 measurement conditions: 10db/div vertical display, 300hz video filter, tek2755ap spectrum analyzer v ref = 0.75v, t a = +25 c, unless otherwise noted.
MAX555 300msps, 12-bit dac with complementary voltage outputs 10 ______________________________________________________________________________________ MAX555 0.1 f 0.1 f 0.1 f 50 ? lines 50 ? 50 ? 1.25ma i ref 1.000v v ref 0.1 f power supply -5.2v 0.1 f 0.1 f 0.4 f 0.1 f d11 (msb) 21, 22 vout vout lgnd terminate unused output ref ref/2 roffset loopcrnt dv ee av ee 7 24, 25 23 20 26 -2v d10 5 -2v d9 4 -2v d8 3 -2v d7 63 -2v d6 62 -2v d5 40, 41 42, 43 44, 45 = analog ground = digital ground 61 -2v -2v 12-bit ecl data word differential ecl clock d4 59 d3 52 -2v d2 51 -2v d1 50 -2v -2v d0 (lsb) 47 clk 56 -2v -2v clk 55 bypass 15 av ee (-5.2v analog) 30 12 lbias agnd dgnd altcompib altcompc 1, 14, 16?9, 27, 28, 29, 31?8, 48, 49, 64 2, 6, 54, 60 57 -2v 50 ? lines 50 ? pulldowns 8 53 dv ee figure 4. typical application
MAX555 300msps, 12-bit dac with complementary voltage outputs ______________________________________________________________________________________ 11 ____________________________________________________________pin configuration 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 n.c. agnd d7 top view d6 d5 dgnd d4 n.c. bypass clk clk dgnd 52 53 49 50 51 dv ee d3 d2 d1 agnd agnd ref roffset ref/2 ref av ee av ee agnd loopcrnt agnd agnd agnd altcompb agnd d0 n.c. vout vout lgnd lgnd vout vout n.c. agnd 33 34 35 36 37 agnd agnd agnd agnd agnd n.c. n.c. d11 dv ee dgnd agnd altcompc *exposed pad on the back of the package must be connected to agnd. agnd n.c. lbias d10 d9 d8 dgnd 48 agnd agnd 64 agnd agnd 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 17 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 MAX555 64 tqfp-ep* *
MAX555 250msps, 12-bit dac with complementary voltage outputs 64l, tqfp.eps maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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